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Confidential Document
DATA IMAGE
CORPORATION
LCD Module Specification
ITEM NO.: TG963220GRNNB-01
Table of Contents 1. COVER & CONTENTS 2. REVISION HISTORY 3. GENERAL SPECIFICATIONS 4. ABSOLUTE MAXIMUM RATINGS 5. ELECTRICAL CHARACTERISTICS 6. ELECTRO-OPTICAL CHARACTERISTICS 7. TIMING CHARACTERISTICS 8. QUALITY ASSURANCE 9. LOT NUMBERING SYSTEM 10. LCM NUMBERING SYSTEM 11. PRECAUTIONS IN USE LCM 12. OUTLINE DRAWING 13. PACKAGE INFORMATION 1 2 3 4 5 5 8 21 24 24 25 26 27
R&D Dept.
Q.C. Dept.
Eng. Dept.
Prod. Dept.
Version:
Issued Date: 2002/8/19
Sheet Code:
Total Pages:
27
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2.
Rev
RECORD OF REVISION
Date Item Page Comment
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3.
GENERAL
SPECIFICATIONS
96 (W) x 0.3 (W) x 0.31 (W) x 35 (W) x 39 (W) x 10 g max. V STN Gray V Reflective Transmissive STN Yellow Transflective Negative 12 O'clock EL Amber Others Others CCFL Blue Green FSTN 32 (H) 0.33 (H) 0.34 (H) 13 (H) 40.02 (H) x Dots mm mm mm 2.2 (T) mm Max.
Display Format : Dot Size : Dot Pitch View Area : General Dimensions : Weight : LCD Type : Polarizer mode :
View Angle : Backlight : Backlight Color :
V 6 O'clock LED Yellow green White
Controller / Driver : Temperature Range :
SED1530TAA Normal V Wide Temperature Operating 0 to 50C Operating -20 to 70C Storage -20 to 70C Storage -30 to 80C
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4. ABSOLUTE MAXIMUM RATINGS 4.1 ELECTRICAL ABSOLUTE MAXIMUM RATINGS
VSS= 0V,
Item Supply Voltage (Logic) Supply Voltage (LCD Driver) Input Voltage Operating Temperature Storage Temperature Symbol VDD-VSS VDD-VEE VI TOP TSTG Min. 0 0 VSS-0.3 -20 -30 Max. 8 16.5 VDD+0.3 70 80
Ta = 25C
Unit V V V
C C
4.2
Item
ENVIRONMENTAL ABSOLUTE MAXIMUM RATINGS
Operating (Min.) -20 Note (2) --4.9M/S
2 2
Storage (Min.) -30 Note(2) --19.6M/S 490M/S
2
Max.) 70
(Max.) 80
Comment Note (1) Without Condensation XYZ Direction XYZ Direction
Ambient Temp Humidity Vibration Shock
29.4M/S
2
Note(1) Ta = 0C : 50Hr Max. Note(2) Ta 40C : 90% RH Max. Ta 40C : Absolute humidity must be lower than the humidity of 90% RH at 40C.
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5.
Item
ELECTRICAL CHARACTERISTICS
Symbol VDD-VSS 0C Condition Min. 2.7 5.2 4.7 4.2 VSS+2.0 VSS -Typ. 3.3 5.5 5.0 4.5 --0.7 Max. 5.5 5.8 5.3 4.8 VDD VSS+0.8 -V mA V Unit V
Supply Voltage (Logic) Supply Voltage (LCD)
VDD-VEE
25C 50C
Input Voltage Logic Supply Current
VIH VIL IDD
--
6. ELECTRO-OPTICAL CHARACTERISTICS
ITEM Rise Time Symbol Tr Condition 0C 25C 0C 25C 25C 25C & CR2 25C 2 60 90 -Min. Typ. -130 -180 5 --70 Max. -260 -360 ----Degree Hz Unit ms Note (1) ms Note (3) Note (2) Ref.
Fall Time Contrast View Angle Frame Frequency
Tf CR 1~2 1, 2 Ff
Note (1) & (2) : See next page Note (3) : Contrast ratio is defined under the following condition: CR= Brightness of non-selected condition Brightness of selected condition ( a ). ( b ). ( c ). ( d ). Temperature ---------- 25C Frame frequency ---- 70Hz Viewing angle -------- = 0, = 0 Operating voltage --- 5.0V
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Note (1) Response time is measured as the shortest period of time possible between the change in state of an LCD segment as demonstrated below: +Vop 1/f F 0
-Vop 90% 100% 10% tr Condition: ( a ) . Temperature ---------------25C ( b ) . Frame frequency --------- 70Hz ( c ) . View Angle ----------------- = 0, =0 ( d ) . Operating voltage -------- 5.0V Note (2) Definition of View Angle Top - Bottom direction Top 1 2 Right -- Left direction 2 1 tf
Bottom
Left
Right
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7. TIMING CHARACTERISTICS
AC Characteristics
(1)System buses Read/write characteristics I (8080series microprocessor)
A0 tAW8 CS1 (CS2="1") WR,RD tCCHW tCCHR tDS8 D0 ~ D7 (WRITE) D0 ~ D7 (READ)
VDD=5.0V10%,Ta=-40 to +85C
tAH8 tCYC8
tCCLW tCCLR
tDH8 tCH8
tACC8
Parameter
Address hold time Address setup time System cycle time Control L pulse width(WR) Control L pulse width(RD) Control H pulse width(WR) Control H pulse width(RD) Data setup time Data hold time RD access time Output disable time
Signal
A0
Symbol
tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tCH8
Condition
Min.
10 10 166 30 70 100 70 20 10 -10
Max.
---------70 50
Unit
ns ns ns ns ns ns ns ns ns ns ns
WR RD WR RD D0 to D7
CL=100pF
VDD=2.7V to 4.5V,Ta= - 40 to +85C
Parameter
Address hold time Address setup time System cycle time Control L pulse width(WR) Control L pulse width(RD) Control H pulse width(WR) Control H pulse width(RD) Data setup time Data hold time RD access time Output disable time
Signal
A0
Symbol
tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tCH8
Condition
Min.
19 15 450 60 140 200 140 40 15 -10
Max.
---------140 100
Unit
ns ns ns ns ns ns ns ns ns ns ns
WR RD WR RD D0 to D7
CL=100pF
Notes:1.The input signal rise/fall time (tr,tf) is specified at 15 ns or less. When system cycle time is used at a high speed, it is specified by tr+tf (tCYC8 - tCCLW ) or tr+tf(tCYC8 - tCCLR- tCCHR). 2.Every timing is specified on the basis of 20% and 80% of VDD . 3. tEWHR and tEWHW are specified by the overlap period in which CS1 is "0"(CS="1") and WR and RD are"0".
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(2)System buses
Read/write characteristics II (6800-series microprocessor)
A0 R/W CS1 (CS2="1")
tAW6 tCYC6 tEWHW tEWHR
tAH6
tEWLW tEWLR
E tDS6 D0 ~ D7 (WR1TE) D0 ~ D7 (READ)
VDD=5.0V10%,Ta=-40 to +85C
tDH6 tOH6
tACC6
Parameter
System cycle time Address hold time Address setup time Data setup time Data hold time Output disable time Access time Enable Low pulse width Enable High pulse width
Signal
A0 W/R D0 to D7 READ WRITE READ WRITE
Symbol
tCYC6 tAH6 tAW6 tDS6 tDH6 tOH6 tACC6
Condition
Min.
166 10 10 20 10 10 -70 30 70 100
Max.
-----50 70 -----
Unit
ns ns ns ns ns ns ns ns ns ns ns
CL=100pF
E E
tEWHR tEWHW tEWLR tEWLW Symbol
tCYC6 tAW6 tAH6 tDS6 tDH6 tOH6 tACC6
VDD=2.7V to 4.5V,Ta=-40 to +85C
Parameter
System cycle time Address hold time Address setup time Data setup time Data hold time Output disable time Access time Enable Low pulse width Enable High pulse width
Signal
A0 R/ W D0 to D7 READ WRITE READ WRITE
Condition
Min.
450 15 19 40 15 10 -140 60 140 200
Max.
-----100 140 -----
Unit
ns ns ns ns ns ns ns ns ns ns ns
CL=100pF
E E
tEWHR tEWHW tEWLR tEWLW
Notes:1.The input signal rise/fall time (tr,tf) is specified at 15 ns or less. When system cycle time is used at a high speed, it is specified by tr+tf(tCYC6 - tEWLW - tEWHW ) or tr+tf(tCYC6 - tEWLR- tEWHR). 2.Every timing is specified on the basis of 20% and 80% of VDD . 3. tEWHR and tEWHW are specified by the overlap period in which CS1 is "0"(CS2="1") and E is "1".
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(3)System buses CS1 (CS2="1") tSAS A0 tSCYC tSLW SCL SI
VDD=5.0V10%,Ta=-40 to +85C
tCSS
tCSH tSAH
tSHW tr tSDS tSDH
tf
Parameter
System clock cycle System clock H pulse width System clock L pulse width Address setup time Address hold time Data setup time Data hold time CS serial clock time
Signal
SCL A0 SI CS
Symbol
tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
Condition
Min.
250 100 75 50 200 50 50 30 100
Max.
----------
Unit
ns ns ns ns ns ns ns ns
VDD=2.7V to 4.5V,Ta=-40 to +85C
Parameter
System clock cycle System clock H pulse width System clock L pulse width Address setup time Address hold time Data setup time Data hold time CS serial clock time
Signal
SCL A0 SI CS
Symbol
tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
Condition
Min.
500 200 150 100 400 100 100 60 200
Max.
----------
Unit
ns ns ns ns ns ns ns ns
Notes:1.The input signal rise and fall times must be within 15 nanoseconds. 2.All signal timings are limited based on 20% and 80% of VDD voltage.
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(4) Display control timing CL (OUT) FR tDOH DYO Output timing Parameter
FR delay time DYO "H" delay time DYO "L" delay time
tDFR tDOL
VDD=5.0V 10%,Ta=-40 to +85C
Signal
FR DYO
Symbol
tDFR tDOH tDOL
Condition
CL=50pF
Min.
----
Typ
10 40 40
Max. Unit
40 100 100 ns ns ns
Output timing Parameter
FR delay time DYO "H" delay time DYO "L" delay time
VSS=0V, VDD=2.7V 4.5V,Ta=to 40 to +85C
Signal
FR DYO
Symbol
tDFR tDOH tDOL
Condition
CL=50pF
Min.
----
Typ
15 70 70
Max. Unit
80 200 200 ns ns ns
Notes:1.The output timing is valid in master mode. 2.Every timing is specified on the basis of 20% and 80% of VDD.
(5) Reset timing tRW RES tR
lnternal circuit status
During reset
End of reset
VDD=5.0V 10%,Ta=-40 to +85C
Parameter
Reset time Reset low pulse width
Signal
RES
Symbol tR tRW
Condition
Min.
0.5 0.5
Typ ---
Max. Unit s -s --
VDD=2.7V to 4.5V,Ta=-40 to +85C
Parameter
Reset time Reset low pulse width
Signal
RES
Symbol tR tRW
Condition
Min.
1.0 1.0
Typ ---
Max. Unit s -s --
Notes:1.The reset timing is specified on the basis of 20% and 80% of VDD.
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7.1. PIN DESCRIPTON
Power Supply Name
VDD VSS V1,V2 V3,V4 V5
I/O
Supply Supply Supply
Description
+5V power supply. Connect to microprocessor power supply pin VCC. Ground LCD driver supply voltages. The voltage determined by LCD cell is impedance-converted by a resistive driver or an operational amplifier for application. Voltages should be the following relationship: VDDV1V2V3V4V5 When the 0n-chip operating power circuit is on, the following voltages are given to V1 to V4 by the on-chip power circuit. Voltage selection is performed by the Set LCD Bias command. SED 1530 1/5V5 1/6V5 2/5V5 2/6V5 3/5V5 4/6V5 4/5V5 5/6V5
Number of pins
2 1 6
V1 V2 V3 V4
LCD Driver Supplies Name
CAP1+ CAP1CAP2+ CAP2CAP3VOUT VR
I/O
O O O O O O I
Description
DC/DC voltage converter capacitor 1 positive connection DC/DC voltage converter capacitor 1 negative connection DC/DC voltage converter capacitor 2 positive connection DC/DC voltage converter capacitor 2 negative connection DC/DC voltage converter capacitor 1 negative connection DC/DC voltage converter output Voltage adjustment pin. Applies voltage between VDD and V5 using a resistive divider.
Number of pins 1 1 1 1 1 1 1
Microprocessor Interface Name
D0 to D7 (SI) (SCL) A0 I
I/O
I/O
Description
8-bit bi-directional data bus to be connected to the standard 8-bit or 16-bit microprocessor data bus. When the serial interface selects; D7:Serial data input(SI) D6:Serial clock input (SCL) Control/display data flag input. It is connected to the LSB of microprocessor address bus. When low, the data on D0 to D7 is control data. When high, the data on D0 to D7 is display data. When RES is caused to go low, initialization is executed. A reset operation is performed at the RES signal level.
Number of pins 8
1 1 2 1
RES CS1 CS2 RD (E) I I
Chip select input. Data input/output is enabled when-CS1 is low and CS2 is high. When chip select is non-active, D0 to D7 will be "HZ". When interfacing to an 8080 series microprocessor: Active low. This input connects the RD signal of the 8080 series microprocessor . While this signal is low, the SED1530 series data bus output is enabled. When interfacing to a 6800 series microprocessor: Active high. This is used as an enable clock input pin of the 6800 series microprocessor. Write enable input. When interfacing to an 8080-series microprocessor, WR is active low. When interfacing to an 6800-series microprocessor, it will be read mode when R/W is high and it will be write mode when R/W is low. R/W= "1" :Read R/W= "0" :Write
WR (R/W)
I
1
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Name
C86
I/O
I
Description
Microprocessor interface select terminal. C86=high: 6800 series microprocessor interface C86=low: 8080 series microprocessor interface Serial data input/parallel data input select pin. P/S "H" "L" Chip select Data/command CS1,CS2 CS1,CS2 A0 A0 Data Read/write Serial clock D0-D7 SI RD,WR Write only -SCL(D6)
Number of pins 1
P/S
I
1
*In serial mode, no data can be read from RAM. When P/S= low, D0 to D5 are HZ and RD and WR must be fixed high or low
7.2. LCD Driver Outputs
Name
M/S
I/O
I
Description
SED1530 series master/slave mode select input. When a necessary signal is output to the LCD, the master operation is synchronized with the LCD system, while when a necessary signal is input to the LCD, the slave operation is synchronized with the LCD system. M/S= high : Master operation M/S= low : Slave operation The following is provided depending on the M/S status. Power supply CL FR DYO FRS DOF circuit Master Enabled Enabled Output Output Output Output Output SED153*D** Slave Disabled Disabled Input Input HZ HZ Input Model Status OSC circuit
Number of pins
1
CL
I/O
Display Clock input/output. When the SED1530 series selects Master/ slave mode, each CL pin is connected. When it is used in combination with the common driver, this input/output is connected to common driver YSCL pin. M/S= high: Output M/S= low: input LCD AC signal input/output. When the SED1530 series selects master/ slave mode, each FR pin is connected. When the SED1530 series selects master mode this input/output is connected to the common driver FR pin. M/S= high: Output M/S= low: input Common drive signal output. This output is enabled for only at master operation and connects to the common driver DIO pin. It becomes HZ at slave operation. Internal power supply voltage monitor output. LCD blanking control input/output. When the SED1530 series selects master/slave mode, the respective DOF pin is connected. When it is used in combination with the common driver (SED1635), this output/ input is connected to the common driver DOFF pin. M/S= high: Output M/S= low: input Static drive output. This is enabled only at master operation and used together with the FR pin. This output becomes HZ at slave operation.
1
FR
I/O
1
DYO
I/O
1
VS1 DOF
O I/O
1 1
FRS
O
1
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Name
On (SEG n) (Com n)
I/O
O the model.
Description
LCD drive output. The following assignment is made depending on
Number of pins
SEG SED 1530D0* SED 1530DA* SED 1530DF* O0~O99 O16~O115
COM O100~O131 O0~O15,O116~O131
SEG output. LCD segment drive output. One of VDD,V2,V3 and V5 levels is selected by combination of the contents of display RAM and FR signal. On output voltage Normal display VDD V5 V2 V3 VDD Reverse display V2 V3 VDD V5
RAM data H 0 Power save
FR H L H L --
COM output. LCD common drive output. One of VDD,V1,V4 and V5 levels is selected by combination of scan data and FR signal. Scan data H L Power save COMS O FR H L H L -On output voltage V5 VDD V1 V4 VDD
Indicator COM output. When it is not used, it is made open. Effective only with the SED1530,SED1532,SED1533 and SED1534 and ``HZ" with the SED1531. When multiple numbers of the SED1530,SED1532,SED1533 and SED1534 are used, the same COMS signal is output to both master and slave units.
Total
172
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7.3. VOLTAGE GENERATOR CIRCUIT
When the on-chip power circuit is used VDD When the on-chip power circuit is used VDD
M/S
VSS VSS
C1 C1 C1 C1
M/S
VSS VSS
CAP3CAP1+ CAP1CAP2+ CAP2VOUT V5 VR
CAP3CAP1+ CAP1CAP2+ CAP2VOUT
R3 R2
VDD
SED1530 series
VDD
V5 VR
SED1530 series
R1
VDD V1 V2 V3 V4 V5
VDD V1 V2 V3 V4 V5
C2
External power supply
Reference setup value: SED1530 V5-7 to -9V SED1531 V5-11 to -13V (variable) SED1532 V5-11 to -13V (variable) SED1530
C1 C2 R1 R2 R3 LCD SIZE
Reset Circuit
When the RES input goes low, this LSI is initialized. Initialized status 1.Display OFF 2.Normal display 3.ADC select: Normal display (ADC command D0=low) 4.Read modify write OFF 5.Power control register (D2, D1, D0)=(0,0,0) 6.Register data clear in serial interface 7.LCD power supply bias ratio 1/6(SED1530), 1/8(SED1531, SED1532) 8.static indicator: OFF 9.Display start line register set at line 1 10.Column address counter set at address 0 11. Page address register set at page 0 12.Output status register (D3)=(0) 13. Electronic control register set at 0 14.Test command OFF As seen in Microprocessor Interface (Reference Example), connect The RES pin to the reset pin of the microprocessor and initialize the microprocessor at the same time. In case the SED1530 series does not use the internal LCD power Supply circuit, the RES must be low when the external LCD power Supply is turned on. When RES goes low, each register is cleared and set to the above Initialized status. However, it has no effect on the oscillator circuit And output pins ( FR, CL, DYO, D0 to D7). The initialization by RES pin signal is always required during Power-on. If the control signal from the MPU is HZ, an over current May flow through the IC. A protection is required to prevent the HZ Signal at the input pin during power-on. Be sure to initialize it by RES pin when turning on the power supply. When the reset command is used, only parameters 8 to 14 in the Above initialization are executed.
SED1531 1.0~4.7uF 0.47~1.0uf 1M 200 K 4M 32x64mm
SED1532 1.0~4.7uF 0.47~1.0uf 1M 200 K 4M 32x100mm
1.0~4.7uf 0.22~0.47uf 700 K 200 K 1.6M 16x50mm
DOT 32x100 64x128 64x200 CONFIGURATON *1: As the input impedance of VR is high, a noise protection using short wire and cable shied is required. *2: C1 and C2 depend on the capacity of the LCD panel to be driven. Seta value so that the LCD drive voltage may be stable. [Setup example] Turn on the voltage regulator and voltage follower and give an external voltage to VOUT. Display a horizontal-stripe LCD heavy load pattern and determine C2 so that the LCD drive voltage (V1 to V5) may be stable. However, the capacity value of C2 must be all equal. Next, turn on all the on-board power supplies and determine C1. *3:LCD SIZE means the length and breadth of the display portion of the LCD panel.
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7.4. MICROPROCESSOR INTERFACE (Reference example)
The SED1530 series chips directly connect to 8080 and 6800-series microprocessors. Also serial interfacing requires less signal lines between them. When multiple chips are used in the SED 1530 series they can be connected to the microprocessor and one of them can be selected by Chip Select.
8080-series microprocessors
VDD VCC A0 A1 to A7 IORQ Decoder AO CS1 CS2 SED 1530 DO to D7 RD WR GND RES RESET VSS DO to D7 RD WR RES VSS P/S VSS VDD VDD C86
MPU
6800-series microprocessors
VDD
VCC A0 A1 to A15 VMA Decoder AO CS1 CS2 SED 1530 DO to D7 E R/W GND RES RESET VSS DO to D7 E R/W RES VSS P/S
VDD
C86
VDD
MPU
VDD
serial interface
VDD VCC A0 A1 to A7 Decoder AO CS1 CS2 SED 1530 Port 1 Port 2 GND RES RESET VSS SI SCL RES P/S
VDD
C86
MPU
VDD
or GND
VSS
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7.5 FUNCTIONAL DESCRIPTION
Microprocessor Interface Interface type selection
The SED1530 series can transfer data via 8-bit bi-directional data buses (D7 to D0) or via serial data input (SI). When high or low is selected for the polarity of P/S pin,either8-bit parallel data input or serial data input can be selected as shown in Table 1. When serial data input is selected, RAM data cannot be read out.
P/S H L
Type Parallel input Serial input
CS1 CS1 CS1
CS2 CS2 CS2
A0 A0 A0
Table 1 RD RD -
WR WR -
C86 C86 -
D7 D6 D0 to D5 D7 D6 D0 to D5 SI SCL (HZ) "-" must always be high or low.
Parallel input When the SED1530 series selects parallel input(P/S= high),the 8080 series microprocessor or 6800 series microprocessor can be selected by causing the C86 pin to go high or low as shown in Table2.
C86 H L
Type 6800 microprocessor bus 8080 microprocessor bus
CS1 CS1 CS1
CS2 CS2 CS2
A0 A0 A0
Table2 RD E RD
WR R/W R/W
D0 to D7 D0 to D7 D0 to D7
Data Bus Signals
The SED1530 series identifies the data bus signal according to A0,E,R/W,(RD,WR) signals.
Common A0 1 1 0 0
6800 processor (R/W) 1 0 1 0
Table3 8080 processor RD WR 0 1 1 0 0 1 1 0
Function Reads display data. Writes display data. Reads status. Writes control data in internal register. (Command)
Serial Interface (P/S is low)
The aerial interface consists of an 8-bit shift register and a 3-bit counter. The serial data input and serial clock input are enabled when CS1 is low and CS2 is high (in chip select status). When chip is not selected, the shift register and counter are rest. Serial data of D7,D6,...,D0 is read at D7 in this sequence when serial clock (SCL) goes high. They are converted Into 8-bit parallel data and processed on rising edge of every eighth serial clock signal. The serial data input (SI) is determined to be the display data when A0 is high, and it is control data when A0 is low A0 is read on rising edge of every eighth clock signal. Figure 1 shows a timing chart of serial interface signals. The serial clock signal must be terminated correctly against termination reflection and ambient noise. Operation checkout on the actual machine is recommended.
CS1 CS2 SI SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1
A0
Figure 1
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7.6. Column Address Counter
This is a 8bit presettable counter that provides column address to the display RAM(refer to Figure 4). It is incremented by 1 when a Read/write command is entered. However, the counter is not incremented but locked if a non-existing address above 84H is specified. It is unlocked when a column address is set again. The Column Address counter is independent of Page Address register. When ADC Select command is issued to display inverse display, the Column address decoder inverts the relationship between RAM Column address and display segment output. RAM area dedicate to the indicator, and display data D0 is only valid.
Display Data RAM
Page Address Register
This is a 4-bit page address register that provides page address to the display RAM (refer to Figure 4). The microprocessor issues Set Page Address command to change the page and access to another Page. Page address 8 (D3 is high, but D2, D1 and D0 are low) is
The display data RAM stores pixel data for LCD. It is a 65column by 132-row(8-page by 8 bit+1) addressable array. Each pixel can be selected when page and column addresses are specified. The time required to transfer data is very short because the microprocessor enters D0 to D7 corresponding to LCD common lines as shown in Figure 3. Therefore, multiple SED1530's can easily configure a large display having the high flexibility with very few data transmission restriction. The microprocessor writes and reads data to/from the RAM through I/O buffer. As LCD controller operates independently, data can be written into RAM at the same time as data is being displayed, without causing the LCD to flicker.
DO D1 D2 D3 D4
1 0 1 0 0 Display data RAM
COM0 COM1 COM2 COM3 COM4 Display on LCD
7.7. Output Status Selector
The SED1530 series except SED1531 can set a COM output scan direction to reduce restrictions at LCD module assembly. This scan direction is set by setting "1"or "0" in the output status register D3.Fig.5 shows the status. Fig.5 shows the status. LCD output ADC (D0) O0 "0" 0 (H) Column address "1" 83(H) Display data RAM D3 SED1530D0* SED1530DA* SED1530DF* 0 1 0 COM15-----0 SEG100 SEG100 SEG100 SEG100 COM0---------------------COM31 COM31---------------------COM0 COM16----31 COM15-----0 0(H) O131 83(H)
1 COM16----31
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Page address Data D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D0= 0 00 01 02 03 04 05 06 07 Line address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Common output COM 0 COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 COM 9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS
D3, D2 D1,D0 0,0,0,0
Page0
0,0,0,1
Page1
0,0,1,0
Page2
1/64
0,0,1,1
Page3
Start
0,1,0,0
Page4
1/32
0,1,0,1
Page5
0,1,1,0
Page6
0,1,1,1
Page7
1,0,0,0 Column address
Page8 80 81 82 83
ADC
Page 8 is accessed during 1/65 or 1/33 duty.
D0= 1 83
7D
7C
7E
7F
03
02 O129
01 O130
82
81
80
O128
O131
LCD OUT
O0
O1
O2
O4
O5
O6
O7
O3
00
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Command (1)Display ON/OFF (2)Initial Display Line (3)Set page Address (4)Set column Address 4 higher bits (4)Set column Address 4 higher bits (5)Read Status (6)Write Display Data (7) Read Display Data (8)ADC Select
Code A0 0 0 0 0 0 0 1 1 0 RD 1 1 1 1 1 0 1 0 1 WR 0 0 0 0 0 1 0 1 0 D7 1 0 1 0 0 Status Write data Read data 1 0 1
0
D6 0 1 0 0 0
D5 1
D4 0
D3 1
D2 1
D1 1
D0 0 1
Function Turns on LCD panel when goes high, and turns off when goes low. Specifies RAM display line for COM0. Sets the display RAM page in Page Address register. Sets 4 high bits of column address of display RAM in register. Sets 4 lower bits of column address of display RAM in register. Reads the sets information. Writes data in display RAM. Read data from display RAM.
Start display address 1 0 0 1 1 0 Page address Higher Column address Lower Column address 0 0 0 0
0
0
0
0 1
(9)Normal/Reverse Display (10)Entire Display ON/OFF (11)Set LCD Bias (12)Read-Modify-Write
0 0 0 0
1 1 1 1
0 0 0 0
1 1 1 1
0 0 0 1
1 1 1 1
0 0 0 0
0 0 0 0
1 1 0 0
1 0 1 0
0 1 0 1 0 1 0
Sets normal relationship between RAM column address and segment driver when low, but reverses the relationship when high. Normal indication when low, but full indication when high. Selects normal display(0) or Entire Display ON (1). Sets LCD drive voltage bias ratio. Increments Column Address counter during each write when high and during each read when low. Releases the Read-Modify-Write. Resets internal functions. Selects COM output scan direction. *Invalid data Selects the power circuit operation mode. Sets V5 output voltage to Electronic control register. Selects standby status. 0:OFF 1:ON Compound command of display OFF and entire display ON IC Test command Do not use!
(13)End (14)Reset (15) Set Output Status Register (16) Set Power Control (17)Set Electronic Control Register (18)Set Standby (19) Power Save (20)Test Command
0 0 0 0 0 0 0
1 1 1 1 1 1 1
0 0 0 0 0 0 0
1 1 1 0 1 1 1
1 1 1 0 0 0 1
1 1 0 1 0 1 1
0 0 0 0
1 0 0 1
1 0 *
1 1 *
0 0 *
Operation status
Electronic control value 0 1 1 * 1 * 0 * 0 1 *
Note: Do not use any other command, or the system malfunction may result.
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8.
QUALITY ASSURANCE 8.1 Test Condition
8.1.1 Temperature and Humidity(Ambient Temperature) Temperature : 20 5C Humidity : 65 5% 8.1.2 Operation Unless specified otherwise, test will be conducted with LCM in operation. 8.1.3 Container Unless specified otherwise, vibration test will be conducted on module only. 8.1.4 Test Frequency Single cycle. 8.1.5 Test Method
No. 1 2 3 4 5 6 7
Parameter High Temperature Operating Low Temperature Operating High Temperature Storage Low Temperature Storage Vibration Test (Non-operation state) Damp Proof Test (Non-operation state) Shock Test (Non-operation state)
Conditions 50 2 C 0 2 C 70 2 C -20 2 C Total fixed amplitude : 1.5mm Vibration Frequency : 10 ~ 55Hz One cycle 60 seconds to 3 directions of X.Y.Z. for each 15 minutes 40C 2C, 90~95%RH, 96h
Regulations Note 3 Note 3 Note 3 Note 3 Note 3
Note 1,2 Note 3
To be measured after dropping from 60cm high once concrete surface in packing state Note 1: Returned under normal temperature and humidity for 4 hours. Note 2: No dew condensation to be observed. Note 3: No change on display and in operation under the test condition
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8.2 Inspection condition
8.2.1 Inspection conditions The LCD shall be inspected under 40W white fluorescent light.
45
8.2.2 Definition of applicable Zones
B LCD A BEZEL PCB
A : Display Area B : Non-Display Area
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8.2.3 Inspection Parameters
No. Parameter Black or White spots Zone Dimension D < 0.15 0.15 D< 0.2 0.2 D 0.25 D 0.3 Acceptable Class number Of Defects A B 4 4 Minor 2 2 0 1 D = (Long + Short) / 2 AQL Level Criteria
1
2.5 * : Disregard
2
Scratch,
Substances Class Acceptable Of number X (mm) Y(mm) Defects A B 0.04 W 4 4 3.0 L 0.06 W Minor 2 3 2.0 L 0.08 W 0 1 0.1 < W X : Length Y : Width : Disregard Total defects should not exceed 4/module Zone AQL Level
2.5
3
Air Bubbles (between glass & polarizer) Zone Dimension D 0.15 0.15 < D 0.25 Acceptable number A B 2 Class of Defects Minor AQL Level
2.5
0 1 0.25 < D : Disregard Total defects shall not excess 3/module.
4
Uniformity of Pixel
(1)
Pixel shape (with Dent) 0.152
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(2)
Pixel shape ( with Projection)
Should not be connected to next pixel 0.152 (3) Pin hole X
4
Uniformity of Pixel
Y ( X + Y )/2 0.02mm (Less than 0.1 mm is no counted) (4) Deformation
X ( X + Y ) / 2 0.3mm
Y Total acceptable number : 1/pixel, 5/cell Definition It is a defect that is likely to result in failure or to reduce materially the usability of the product for the intended function. It is a defect that is likely to assembly size and not result in functioning problem. It is a defect that will not result in functioning problem with deviation classified.
Major Class of defects Minor
AQL 0.65% AQL 1.00% AQL 2.5%
8.3 Sampling Condition
Unless otherwise agree in written, the sampling inspection shall be applied to the incoming inspection of customer. Lot size: Quantity of shipment lot per model. Sampling type: normal inspection, single sampling Inspection level: Level II Sampling table: MIL-STD-105E
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9.
LOT NUMBERING SYSTEM
9 7 4 2 Production week number Production year
10.
LCM NUMBERING SYSTEM TG 963220 G R N N B - 01
VERSION :01 View direction & Temp. Range A-Bottom view 6H & Normal temp. B-Bottom view 6H & Wide temp. C-Top View & Normal temp. D-Top View & Wide temp.
Backlight Color
B -Blue W -White N -None
Backlight
S -edge light LED B/L E -EL N -No Back light
MODE
M - transmissive F - transflective R - Reflective N - Negative
LCD type
G - STN Gray S -STN Yellow F - FSTN
Series code 963220 -96 Dots X32 Dot, 2 LCD type, 0 PCB type Model type
CM - Character Module GM - Graphic Module TG-Single TAB/COG Graphic Module TX-Custom Single TAB/COG Graphic Module
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11.
PRECAUTION FOR USING LCM
(5) The normal static prevention measures should be observed for work clothes and working benches; for the latter conductive (rubber) mat is recommended. (6). Since dry air is inductive to static, a relative humidity of 50-60% is recommended. 2.3 Soldering (1). Solder only to the I/O terminals. (2). Use only soldering irons with proper grounding and no leakage. (3). Soldering temperature : 280C 10C (4). Soldering time: 3 to 4 sec. (5). Use eutectic solder with resin flux fill. (6). If flux is used, the LCD surface should be covered to avoid flux spatters. Flux residue should be removed after wards. 2.4 Operation (1). The viewing angle can be adjusted by varying the LCD driving voltage V0. (2). Driving voltage should be kept within specified range; excess voltage shortens display life. (3). Response time increases with decrease in temperature. (4). Display may turn black or dark blue at temperatures above its operational range; this is (however not pressing on the viewing area) may cause the segments to appear "fractured". (5). Mechanical disturbance during operation (such as pressing on the viewing area) may cause the segments to appear "fractured". 2.5 Storage If any fluid leaks out of a damaged glass cell, wash off any human part that comes into contact with soap and water. Never swallow the fluid. The toxicity is extremely low but caution should be exercised at all the time. 2.6 Limited Warranty Unless otherwise agreed between DATA IMAGE and customer, DATA IMAGE will replace or repair any of its LCD and LCM which is found to be defective electrically and visually when inspected in accordance with DATA IMAGE acceptance standards, for a period on one year from date of shipment. Confirmation of such date shall be based on freight documents. The warranty liability of DATA IMAGE is limited to repair and/or replacement on the terms set forth above. DATA IMAGE will not responsible for any subsequent or consequential events.
1. LIQUID CRYSTAL DISPLAY (LCD) LCD is made up of glass, organic sealant, organic fluid, and polymer based polarizers. The following precautions should be taken when handing, (1). Keep the temperature within range of use and storage. Excessive temperature and humidity could cause polarization degredation, polarizer peel off or bubble. (2). Do not contact the exposed polarizers with anything harder than an HB pencil lead. To clean dust off the display surface, wipe gently with cotton, chamois or other soft material soaked in petroleum benzin. (3). Wipe off saliva or water drops immediately. Contact with water over a long period of time may cause polarizer deformation or color fading, while an active LCD with water condensation on its surface will cause corrosion of ITO electrodes. (4). Glass can be easily chipped or cracked from rough handling, especially at corners and edges. (5). Do not drive LCD with DC voltage. 2. Liquid Crystal Display Modules 2.1 Mechanical Considerations LCM are assembled and adjusted with a high degree of precision. Avoid excessive shocks and do not make any alterations or modifications. The following should be noted. (1). Do not tamper in any way with the tabs on the metal frame. (2). Do not modify the PCB by drilling extra holes, changing its outline, moving its components or modifying its pattern. (3). Do not touch the elastomer connector, especially insert an backlight panel (for example, EL). (4). When mounting a LCM make sure that the PCB is not under any stress such as bending or twisting . Elastomer contacts are very delicate and missing pixels could result from slight dislocation of any of the elements. (5). Avoid pressing on the metal bezel, otherwise the elastomer connector could be deformed and lose contact, resulting in missing pixels. 2.2. Static Electricity LCM contains CMOS LSI's and the same precaution for such devices should apply, namely (1). The operator should be grounded whenever he/she comes into contact with the module. Never touch any of the conductive parts such as the LSI pads, the copper leads on the PCB and the interface terminals with any parts of the human body. (2). The modules should be kept in antistatic bags or other containers resistant to static for storage. (3). Only properly grounded soldering irons should be used. (4). If an electric screwdriver is used, it should be well grounded and shielded from commutator sparks.
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12 OUTLINE DRAWING
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13. PACKAGE INFORMATION
Module
Anti-static PET tray
Carton
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